1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit manufacturing and, more particularly to a method of forming device isolation regions on a semiconductor substrate by using PECVD and to a method of removing residual carbon deposits from an intermediate semiconductor device structure.
2. Description of the Related Art
Integrated circuits fabricated on semiconductor substrates for large scale integration require multiple levels of metal interconnections to electrically interconnect the discrete layers of semiconductor devices on the semiconductor chips. Today several million devices can be fabricated in a single chip, for example, the mega-bit memory chips which are commonly used today in personal mobile and in other applications.
Devices of semiconductor typically include semiconductor substrate and a plurality of adjacent, active devices that are electrically isolated from one another. With the increased circuit density, effective isolation between active devices becomes increasingly important. One isolation technique is local oxidation of silicon isolation (LOCOS), which forms a recessed oxide layer in non-active regions of the semiconductor substrate to isolate the active devices. The oxide layer is conventionally formed by patterning a hard mask and thermal oxidation of the substrate.
The above described conventional LOCOS technique has a number of disadvantages, which become rather unacceptable when attempting to apply this technique to the fabrication of sub-micron devices. First, the oxidization of silicon happens not only in the vertical direction but also in the horizontal direction. As a result, a part of the field oxide grows under adjacent silicon nitride or other hard mask layers and lifts it up. This is termed the “bird's beak effect” by persons skilled in the art. Secondly, due to the stresses caused by the bird's beak effect, a part of nitride hard mask in the compressed regions of silicon nitride layer diffuses to adjacent tensile strained regions at the interface of the pad oxide layer and the substrate, and forms a silicon-nitride-like region. In subsequent process steps of forming gate oxides, due to the mask effect of the silicon-nitride-like layer, the gate oxides will be thinner than they should be. This is termed the “white ribbon effect” because a white ribbon will appear at the edges of active regions under optical microscopes.
An alternative technique is trench isolation, which involves etching trenches in nonactive regions of a semiconductor substrate. Trench isolation is referred to as shallow trench isolation (STI) or deep trench isolation (DTI), depending on the depth of the trench etched in the semiconductor substrate. DTI structures, which typically have a depth of greater than approximately 3 microns, are used to isolate active devices such as N-wells and P-wells. Shallow trench structures are used to isolate adjacent electronic devices, such as transistors, and often have a depth of less than approximately 1 micron. The trenches are filled with a deposited insulative dielectric material, such as a silicon dioxide material. The filled trenches are known in the art as trench isolation or trench isolation regions. The trench is typically filled with the silicon dioxide material by a chemical vapor deposition (CVD) technique, such as high density plasma CVD. In CVD, gaseous precursors of the silicon dioxide material are supplied to a surface of the semiconductor substrate. The gaseous precursors react with the surface to form a film or layer of the silicon dioxide material.
Trench isolation provides a smaller isolation area and better surface planarization than LOCOS. While trench isolation provides these advantages, undesirable voids can be formed in the silicon dioxide material as the trench fills because the silicon dioxide material tends to stick to the sides and sidewalls of the trench, rather than evenly filling the trench from the bottom to the top. Voids are especially common in deep trenches, such as trenches having a high aspect ratio (depth:width) of greater than approximately 3:1. Voids also commonly form at later stages of the filling process because the trenches, both deep and shallow, become narrower as they fill.
Recently, CVD of flowable oxide material has been developed to reduce the formation of voids. An organic doped silicon oxide film is formed in trenches by supplying a liquid silicon precursor which includes a methyl or ethyl group bond. Often the precursor is supplied while spinning the substrate, such that the resultant process or material is referred to as SOD for spin-on deposition or spin-on dielectric. Furthermore, as the technology shrinks nodes to 45 nm and beyond, the demands for not only gap-filling, but also conformal coating are ever increasing.
In addition, while depositing the flowable oxide material, residual carbon deposits are present in the deposited film if the precursors contain carbon. Carbon in the deposited film causes the film to be soft and porous, which makes the deposited film unstable during subsequent processing, such as etching processes. Also, if the flowable oxide material is used to fill isolation trenches within the semiconductor substrate, the carbon cause device degradation.